Generally a method for manufacturing a silicon wafer comprises a slicing step of slicing a single crystal ingot to obtain a thin disk-shaped wafer; a chamfering step of chamfering a peripheral edge portion of the wafer obtained through the slicing step to prevent cracking and chipping of the wafer; a lapping step of flattening this wafer; an etching step of removing machining deformation remaining in the so chamfered and lapped wafer; a polishing step of making a mirror surface of the wafer; and a cleaning step of cleaning the polished wafer to remove a polishing agent or dust particles deposited thereon. Only the main steps are listed above, and sometimes other steps such as a heat treatment step may be added, or the step sequence may be changed. The silicon wafer manufactured as described above is finally subjected to a quality check, then is packaged in a container for accommodating wafers therein, and is sent to a device fabricating company (or step).
With the manufacturing steps as described above, recently in association with the tendency that devices have been becoming more and more minute, demands for device performance to be achieved have become increasingly severe, and further the silicon wafer is required to have completeness of the crystal quality and cleanliness of the wafer surface.
To satisfy the demands, it is necessary to evaluate quality of the silicon wafer under stringent conditions, and to improve the processing for manufacturing the silicon wafer and fabricating the device using the silicon wafer therein.
In the silicon wafer, completeness of the crystal quality is largely spoiled by existence of impurities, microdefects, strain fields and so on. On the silicon wafer surface, heavy metals, organic materials, particles and surface roughness also cause problems.
As a defect causing a problem in a device fabricating process, there has been known a COP (Crystal Originated Particle) appearing in the vicinity of a surface layer of the wafer. The COP is generally defined as a defect with the size of 0.1 μm or less, but it appears on the wafer surface as a pit, that is, a defect with the size on the order of 0.1 to 0.5 μm which can be observed by processing the wafer with an ammonia-hydrogen peroxide solution (also referred to as a “SCl solution”). These are defects generated when the crystal is pulled.
A FPD (Flow Pattern Defect) having closely related to an oxide film dielectric breakdown strength is a ripple-like defect appearing when preferential etching is performed with an etching liquid based on hydrofluoric acid and potassium bichromate.
There have been known other defects such as a LSTD (Laser Scattering Tomography Defect) detected by the laser scattering tomography, and these defects are microdefects having similar behavior during growth of the crystal.
Further it is known that such defects as an OSF (Oxidation-induced Staking Fault) largely affect performance of a device.
To evaluate these defects, generally preprocessing is performed to a silicon wafer itself prior to start of the evaluation, and then the defects are directly monitored visually, with an electronic microscope or the like.